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700 mhz to 1000 mhz rf vector modulator data sheet ad8340 f eatures cartesian amplitude and phase modulation 700 mhz to 1.0 ghz frequency range continuous magnitude control of ?2 db to ?32 db continuous phase control of 0 to 360 output third - order intercept 24 dbm output 1 db compression point 11 dbm output noi se floor ?149 dbm/hz at full gain adjustable modulation bandwidth up to 230 mhz fast output power disable 4.75 v to 5.25 v single - supply voltage a pplications rf pa linearization/rf predistortion amplitude and phase modulation variable attenuators and pha se shifters cdma2000, gsm/edge linear power amplifiers smart antennas functional block diagram 90 0 vps2 qbbm qbb p rfi p rfim dso p ibbm ibb p rfo p rfom 04699-001 vprf cmo p figure 1 . g eneral d escription the ad8340 vector modulator performs arbitrary amplitude and phase modulation of an rf signal. because the rf signal path is linear, the original modulation is preserved. this part can be used as a general - purpose rf modulator, a variable atten u ator/phase shifter, or a remodulator. the amplit ude can be co n trolled from a maximum of ?2 db to less than ?32 db, and the phase can be shifted continuously over the entire 360 range. for maximum gain, the ad8340 delivers an op1db of 11 dbm, an oip3 of 24 dbm, and an output noise floor of ?149 dbm/hz, independent of phase. it operates over a fr e - quency range of 700 mhz to 1.0 ghz. the baseband inputs in cartesian i and q format control the amplitude and phase modulation imposed on the rf inpu t signal. both i and q inputs are dc - coupled with a 500 mv differential full - scale range. the maximum modulation ban d - width is 230 mhz, which can be reduced by adding external capacitors to limit the noise bandwidth on the control lines. both the rf inpu ts and outputs can be used differentially or single - ended and must be ac - co upled. the rf input and output impedances are nominally 50 ? over the operating frequency range. the dsop pin allows the outpu t stage to be disabled quickly to protect subsequent stages from overdrive. the ad8340 operates off supply voltages from 4.75 v to 5.25 v while consuming approximately 130 ma. the ad8340 is fabricated using the analog devices , inc. proprietary, high performance 25 ghz soi complementary bipolar ic process . it is available in a 24 - lead rohs - compliant lfcsp package and operates over a ?40c to +85c tempera - ture range. evaluation boards are available. rev. c document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specif ications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2004C 2014 analog devices, inc. all rights reserved. technical support www.analog.com
a d8340 data sheet table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 4 esd caution .................................................................................. 4 pin configuration and function descriptions ............................. 5 typical performance characteristics ............................................. 6 theory of operation ...................................................................... 10 rf quadrature generator ......................................................... 10 i - q attenuators and baseband amplifiers .............................. 11 output amplifier ........................................................................ 11 noise and distortion .................................................................. 11 gain and phase accur acy .......................................................... 11 rf frequency range .................................................................. 11 applications information .............................................................. 12 using t he ad8340 ...................................................................... 12 rf input and matching ............................................................. 12 rf output and matching .......................................................... 13 driving the i - q baseband controls ......................................... 13 interfacing to high speed dacs .............................................. 14 cdma2000 application ........................................................... 14 evaluation board ............................................................................ 16 schematic and artwork ............................................................. 18 outline dimensions ....................................................................... 20 ordering guide .......................................................................... 20 r evision history 3/14 rev. b to rev. c added exposed pad notation, figure 2 and table 3 ................... 5 updated outline dimensions ....................................................... 20 changes to ordering guide .......................................................... 20 8/07 rev. a to rev b replaced pin configuration and function descriptions section ........................................................................ 5 changes to figure 30 ...................................................................... 12 changes to figure 39 ...................................................................... 18 7 /07 rev. 0 to rev. a replaced pin configuration and function descriptions section ........................................................................ 5 changes to ordering guide .......................................................... 20 6/04 revision 0: initial ver sion rev. c | page 2 of 20
data sheet ad8340 specifications v s = 5 v, t a = 25c, z o = 50 ?, f = 880 mhz, single - ended, ac - coupled source drive to rfip through 5.6 nh series inductor, rfim ac - coupled through 5.6 nh series inductor to common, differential - to - single - ended conversion at output using 1:1 balun. table 1. parameter conditions min typ max unit overall function frequency range 700 1000 mhz maximum gain maximum gain setpoint for all phase setpoints ?2 db minimum gain v bbi = v bbq = 0 v ?32 db gain control range relative to m aximum gain 30 db phase control range over 30 db control range 360 degrees gain flatness over any 60 mhz bandwidth 0.25 db group delay flatness over any 60 mhz bandwidth 10 ps rf input stage rfim, rfip (pin 21 and pin 22 ) i nput return loss from rfip to cmrf (with 5.6 nh series inductors) 20 db cartesian control interface (i and q) ibbp, ibbm, qbbp, qbbm (pin 16, pin 15, pin 3, pin 4) gain scaling 2 1/v modulation bandwidth 250 mv p - p sinusoidal baseband i nput single - ended 230 mhz second harmonic distortion 250 mv p - p, 1 mhz, sinusoidal baseband input differential 47 dbc third harmonic distortion 250 mv p - p, 1 mhz, sinusoidal baseband input differential 45 dbc step response for gain setp oint from 0.1 to 0.9 (v bbp = 0.5 v, v bbm = 0.55 v to 0.95 v) 45 ns for gain setpoint from 0.9 to 0.1 (v bbp = 0.5 v, v bbm = 0.95 v to 0.55 v) 47 ns rf output stage rfop, rfom (pi n 9 and pin 10) output return loss measured through balun 7.5 db f = 880 mhz gain maximum gain setpoint ?2 db output noise floor maximum gain setpoint, no input ?149 dbm/hz p in = 0 dbm, frequency offset = 20 mhz ?147 dbm/hz output ip3 f1 = 880 mhz, f2 = 877.5 mhz, maximum gain set point 24 dbm acpr is - 95, single carrier, p out = 0 dbm, maximum gain, phase setpoint = 45 62 dbc output 1 db compression point maximum gain 11 dbm power supply vps2 (pin 5, pin 6, pin 14 ); rfop, rfom (pin 9 and pin 1 0 ) positive supp ly voltage 4.75 5 5.25 v total supply current includes load current 110 130 150 ma output disable dsop (pin 13 ) disable threshold 2.5 v maximum attenuation dsop = 5 v 40 db enable response time delay following high -to - low transition until device meets full specifications 15 ns disable response time delay following low -to - high transition until device produces full attenuation 10 ns rev. c | page 3 of 20
a d8340 data sheet absolute maximum rat ings table 2. parameter rating s upply voltage vprf, vps2 5.5 v dsop 5.5 v ibbp, ibbm, qbbp, qbbm 2.5 v rfop, rfom 5.5 v rf input power at maximum gain (50 ) 13 dbm (rfip or rfim, single - ended drive) equivalent voltage 2.8 v p -p internal power dissipation 825 mw ja ( w ith pad soldered to board) 59c/w maximum junction temperature 125c operating temperature range ?40c to +85c storag e temperature range ?65c to +150c lead temperature (soldering , 60 sec) 300c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at t hese or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution rev. c | page 4 of 20
data sheet ad8340 pin configuration and function descrip tions vprf cmrf rfi p rfim cmrf vprf dso p vps2 ibbm ibb p iflm ifl p cmo p cmo p rfom rfo p cmo p cmo p vps2 notes 1. the exposed p ad must be connected t o ground via a low impedance pa th. vps2 qbbm qbb p qflm qfl p 04699-002 2 1 3 4 5 6 18 17 16 15 14 13 8 9 10 1 1 7 12 20 19 21 22 23 24 ad8340 t op view (not to scale) figure 2 . pin configuration table 3 . pin function descriptions pin no. mnemonic description 1; 2 qflp; qflm q baseband input filter pins. connect optional capacitor to redu ce q baseband channel low - pass co r ner frequency. 3; 4 qbbp; qbbm q channel differential baseband inputs. 5, 6, 14; 19, 24 vps2; vprf positive supply voltage , 4.75 v to 5.25 v. 7, 8 , 11 , 1 2 ; 20 , 23 cmop ; cmrf device common. connect via lowest possi ble impedance to external circuit common. 9; 10 rfop ; rfom differential rf outputs. must be ac - coupled. differential impedance 50 nominal. 13 dsop output disable . pull high to disable output stage. 15; 16 ibbm ; ibbp i channel differential baseband inputs. 17; 18 iflm; iflp i baseband input filter pins. co nnect optional capacitor to reduce i baseband channel low - pass corner frequency. 21; 22 rfim; rfip differential rf inputs. must be ac - coupled. differential impedance 50 nominal. epad exposed pad. the exposed pad must be connected to ground via a low impedance path. rev. c | page 5 of 20
a d8340 data sheet typical performance characteristics 04699-003 gain setpoint 0 0.3 0.5 0.9 1.0 0.8 0.7 0.6 0.4 0.2 0.1 gain (db) 0 ?5 ?40 ?10 ?15 ?20 ?25 ?30 ?35 phase setpoint = 180 phase setpoint = 270 phase setpoint = 90 phase setpoint = 0 figure 3 . gain magnitude vs. gain setpoint at different phase setpoints, rf frequency = 880 mhz 04699-004 gain setpoint 4 3 ?6 gain conformance error (db) ?2 ?3 ?4 ?5 0 ?1 2 1 ?7 0 0.1 1.0 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 phase setpoint = 180 phase setpoint = 270 phase setpoint = 315 phase setpoint = 0 phase setpoint = 90 phase setpoint = 45 phase setpoint = 135 phase setpoint = 225 figure 4 . gain conformance error vs. gain se tpoint at different phase setpoints 04699-005 phase setpoint (degrees) 0 ?20 45 gain (db) ?2 ?8 ?12 ?16 ?18 ?4 ?6 ?10 ?14 ?22 ?24 315 270 360 180 90 135 225 0 gain setpoint = 0.1 gain setpoint = 0.5 gain setpoint = 1.0 figure 5 . gain magnitude vs. phase setpoint at different gain setpoints 04699-006 0.4 ?1.6 gain conformance error (db) 0.2 ?0.4 ?0.8 ?1.2 ?1.4 0.0 ?0.2 ?0.6 ?1.0 ?1.8 ?2.0 phase setpoint (degrees) 45 315 270 360 180 90 135 225 0 gain setpoint = 0.1 gain setpoint = 0.5 gain setpoint = 1.0 figure 6 . gain conformance error vs. phase setpoint at different gain setpoints 04699-007 phase setpoint (degrees) 360 150 60 phase (degrees) 330 180 120 90 300 240 270 210 30 0 0 30 60 90 120 150 180 210 240 270 300 330 360 gain setpoint = 1.0 gain setpoint = 0.1 gain setpoint = 0.5 fi gure 7 . phase vs. phase setpoint at different gain setpoints 04699-008 phase setpoint (degrees) 0 45 90 135 360 180 225 270 315 phase error (degrees) 6 4 ?12 2 0 ?2 ?4 ?6 ?8 ?10 gain setpoint = 0.1 gain setpoint = 0.5 gain setpoint = 1.0 figure 8 . phase error vs. phase setpoint at different gain setpoints rev. c | page 6 of 20
data sheet ad8340 04699-009 gain setpoint 0 0.3 0.5 0.9 1.0 0.8 0.7 0.6 0.4 0.2 0.1 noise floor (dbm/hz) ?142 ?143 ?152 ?144 ?145 ?146 ?147 ?148 ?149 ?150 ?151 no rf input rf p in = +5dbm rf p in = ?5dbm rf p in = 0dbm figure 9 . output noise floor vs. gain, no ise in dbm/hz, no carrier, with carrier (20 mhz offset) p in = ?5 dbm , 0 dbm , and +5 dbm 04699-010 frequenc y (mhz) 0 ?14 ?20 gain (db) ?2 ?12 ?16 ?18 ?4 ?8 ?6 ?10 ?22 ?24 700 1000 950 900 850 800 750 gain setpoint = 1.0 gain setpoint = 0.5 gain setpoint = 0.1 figure 10 . gain vs. frequency at different gain setpoints (700 mhz to 1000 mhz), phase setpoint = 0 04699-0 1 1 rf frequenc y (mhz) 700 750 800 850 1000 900 950 ?145 ?146 ?152 ?147 ?148 ?149 ?150 ?151 noise (dbm/hz) figure 11 . output noise floor vs. frequency, maximum gain, no rf c arrier, phase setpoint = 0 04699-012 frequenc y (mhz) 700 750 800 850 1000 900 950 gain fl a tness (db) 0 ?0.5 ?2.5 ?1.0 ?1.5 ?2.0 figure 12 . gain flatness vs. frequency, maximum gain, phase setpoint = 0 04699-013 0 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 100 200 300 400 500 600 700 800 900 1000 differentia l baseband input leve l (mv p-p) (i or q channe l driven a t 1mhz) rf output am sideband power (dbm) fundamen t a l power, 879mhz, 881mhz second baseband harmonic produc t , 878mhz, 882mhz third baseband harmonic produc t , 877mhz, 883mhz figure 13 . baseband harmonic distortion (i and q channel, rf input = 0 dbm, balun and cable loss es of approximately 2 db not accounted for in plot) 04699-014 frequenc y (mhz) 700 750 800 850 1000 900 950 op1db (dbm) 14 12 0 10 8 6 4 2 tem p = ?40c tem p = +85c tem p = +25c figure 14 . output 1 db compression point vs. frequency and temperature, maximum gain, phase setpoint = 0 rev. c | page 7 of 20
a d8340 data sheet 04699-015 frequenc y (mhz) 700 750 800 850 1000 900 950 oip3 (dbm) 30 28 10 26 24 22 20 18 16 14 12 tem p = ?40c tem p = +25c tem p = +85c figure 15 . output ip3 vs. frequency and temperature, maximum gain, i only 04699-016 frequenc y (mhz) 0 50 100 150 400 200 250 300 350 rf output am sideband power (dbm) 0 ?5 ?30 ?10 ?15 ?20 ?25 1v p-p bb input 500mv p-p bb input 200mv p-p bb input figure 16 . i/q modulation bandwidth vs. baseband magnitude 04699-017 phase setpoint (degrees) 14 0 ?6 op1db (dbm) 12 2 ?2 ?4 10 6 8 4 ?8 ?10 315 ?12 360 270 225 180 135 90 45 0 gain setpoint = 1.0 gain setpoint = 0.5 gain setpoint = 0.1 figure 17 . output 1db compression point vs. gain and phase setpoints 04699-018 phase setpoint (degrees) 0 45 90 135 360 180 225 270 315 oip3 (dbm) 30 25 0 20 15 10 5 gain setpoint = 1.0 gain setpoint = 0.5 gain setpoint = 0.1 figure 18 . output ip3 vs. gain and phase setpoints, 2.5 mhz carrier spacing 04699-019 frequenc y (mhz) output power (dbm) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 center 880 mhz 500 khz/div s p an 5 mhz 1 rm rbw 30khz vbw 30khz swt 100ms rf a tt 20db mixer ?10dbm unit dbm ref l v l 0 dbm a desired sideband rf feedthrough undesired sideband second baseband harmonic second baseband harmonic figure 19 . single - sideband performance, 880 mhz, 10 dbm rf input; 1 mhz, 500 mv p - p differential bb drive 04699-020 0 180 30 330 60 90 270 300 120 240 150 210 impedance circle s 1 1 rf port with 5.6nh induc t ors s 1 1 rf port without induc t ors 1.5ghz 1.5ghz 500mhz 500mhz figure 20 . input and output impedance smith chart (with frequency markers) rev. c | page 8 of 20
data sheet ad8340 impedance circle s22 port with 1 t o 1 transformer sdd22 port differentia l 04699-021 0 180 30 330 60 90 270 300 120 240 150 210 1.5ghz 1.5ghz 500mhz 500mhz figure 21 . output imp edance smith chart (with frequency markers) 04699-022 gain setpoint 1.0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 phase error (degrees) 6 4 2 0 ?2 ?4 ?6 ?8 ?10 ?12 ?14 phase setpoint = 0 phase setpoint = 45 phase setpoint = 90 figure 22 . phase error vs. gain setpoint by phase setpoint, 5 v dc, 25c, 880 mhz 04699-023 temper a ture (c) 135 127 supp l y current (ma) 20 134 130 129 128 133 132 131 126 40 30 125 60 70 80 50 ?40 ?30 ?20 ?10 0 10 5.25v 5v 4.75v figure 23 . supply current vs. temperature 04699-024 dso p vo lt age (v) 0 1.5 2.5 4.5 5.0 4.0 3.5 3.0 2.0 1.0 0.5 rf output power (dbm) 0 ?5 ?50 ?10 ?15 ?20 ?25 ?30 ?35 ?40 ?45 figure 24 . power shutdown attenuation 04699-025 ch1 200mv ch3 2.0v m 10.0ns 5.0gs/s a ch2 160mv et 200ps/pt 74.0ns time (10ns/div) cha1/cha3 (v) tek f ast acq sample 3 2v/div 200mv/div rf output dso p figure 25 . power shutdown response time rev. c | page 9 of 20
a d8340 data sheet theory of operation the ad8340 is a linear rf vector modulator with cartesian bas eband controls. in the simplified block diagram shown in figure 26 , the rf signal propagates from the left to the right while baseband controls are placed above and below. the rf input is first split into in - phase ( i) and quadrature (q) comp o - nents. the variable attenuators independently scale the i and q components of the rf input. the attenuator outputs are then summed and buffered to the output. by controlling the relative amounts of i and q components that are su mmed, the ad8340 allows continuous magnitude and phase control of the gain. consider the vector gain representa - tion of the ad8340 exp ressed in polar form in figure 27 . the attenuation factors for the i and q signal components are represented on the x - and y - axis, respectively, by the baseband inputs, v bbi and v bbq . the resultant vector sum repres ents the vector gain, which can also be expressed as a magnitude and phase. by applying different combinations of baseband inputs, any vector gain within the unit circle can be programmed. a change in sign of v bbi or v bbq can be viewed as a change in sign of the gain or as a 180 phase change. the outermost circle represents the maximum gain magnitude of unity. the circle origin implies, in theory, a gain of 0. in practice, circuit mismatches and unavoidable signal feedthrough limit the minimum gain to ap proximately ?40 db. the phase angle between the resultant gain vector and the positive x - axis is d e fined as the phase shift. note that there is a nominal, systematic inse r tion phase through the ad 8340 to which the phase shift is added. in the following discussions, the systematic insertion phase is normalized to 0. the correspondence between the desired gain and phase se t points, gain sp and phase sp , and the cartesian inputs, v bbi and v bbq , is gi ven by simple trigonometric identities . ( ) ( ) o bbq o bbi sp v v v v gain + = ( ) bbi bbq sp v v phase / arctan = v o is the baseband scaling constant (500 mv). v bbi and v bbq are the differential i and q baseband voltages, respectively. note that when evaluating the arctange nt function, the proper phase quadrant must be selected. for example, if the principal value of the arctangent (known as the a rctangent(x)) is used, q uadrant 2 and quadrant 3 woul d be interpreted mistakenly as q uadrant 4 and quadrant 1, respectively. in g eneral, both v bbi and v bbq are needed in co n cert to modulate the gain and the phase. pure amplitude modulation is represented by radial movement of the gain vector tip at a fixed angle, while pure phase modul a - tion is represented by rotation of the tip ar ound the circle at a fixed radius. unlike traditional i - q modulators, the ad8340 is d e signed to have a linear rf signal path from input to output. traditional i - q modulators provide a limited lo carrier path through which any amplitude information is removed. 04699-026 linear a ttenu a t or linear a ttenu a t or v -i v -i 0/90 i-v v bbq q channe l input single-ended or differentia l ,1387= v bbi i channe l input output disable single-ended or differentia l 287387 figure 26 . simplified architecture of the ad8340 04699-027 |a| a +0.5 ?0.5 +0.5 ?0.5 v i v q min gain < ?30db max gain = 0db figure 27 . vector gain repr esentation rf quadrature genera tor the rf input is directly coupled differentially or single - ended ly to the quadrature generator, which consists of a multistage rc polyphase network tuned over the operating frequency range of 700 mhz to 1000 mhz. the recyc ling nature of the polyphase network generates two replicas of the input signal, whi ch are in precise quadrature, that is , 90, to each other. because the passive network is perfectly linear, the amplitude and phase inform a tion contained in the rf input i s transmitted faithfully to both cha n nels. the quadrature outputs are then separately buffered to drive the respective attenuators. the characteristic impedance of the polyphase network is used to set the input impe d ance to the ad8340 . rev. c | page 10 of 20
data sheet ad8340 i - q attenuators and ba seband amplifiers the proprietary linear - responding attenuator structure is an active solution with differential inputs and outputs that offer excellent linearity, low noise, and greater immun ity from mis - matches than other variable attenuator methods. the gain, in linear terms, of the i and q channels is proportional to its control voltage with a scaling factor designed to be 2/v , that is, a full - scale gain setpoint of 1.0 (?2 db) for v bbi (q) of 500 mv. the control voltages can be driven differentially or single - ended ly . the combination of the baseband amplifiers and attenuators allows for maximum modulation bandwidths in excess of 200 mhz. output amplifier the output amplifier accepts the sum of the attenuator outputs and delivers a differential output signal into the external load. the output pins must be pulled up to an external supply, preferably through rf chokes. when the 50 ? load is taken diffe r entially, an o p1db of 11 dbm and o ip3 of 2 4 dbm are achieved at 880 mhz. the output can be taken in single - ended fashion, albeit at lower performance levels. noise and distortion the output noise floor and distortion levels vary with the gain magnitude but do not vary significantly with the phase. at the higher gain magnitude setpoints, the oip3 and the noise floor vary in direct proportion with the gain. at lower gain magn i - tude setpoints, the noise floor levels off while the oip3 conti n ues to vary with the gain. gain and phase accur acy there are numerous ways to express the accuracy of the ad8340. ideally, the gain and phase should precisely follow the setpoints. figure 4 illustrates the gain error in decibels ( db ) from a best fit line, normalized to the gain measured at the gain setpoint = 1.0, for the different phase setpoints. figure 6 shows the gain error in a different form; the phase setpoint is swept from 0 to 360 for different gain setpoints. figure 8 and figure 22 show analo - gous errors for the phase error as a function of gain and phase setpoints. the accuracy clearly depends on the region of operation within the vector gain unit ci rcle. operation very close to the origin generally results in larger errors as the relative accuracy of the i and q vectors degrades. rf frequency range the frequency range on the rf input is limited by the internal polyphase quadrature phase - splitter. the phase - splitter splits the incoming rf input into two signals, 90 out of phase, as previously described in the rf quadrature generator section. this polyphase network has been designed to ensure robust quadrature a ccuracy over standard fabrication process param e ter variations for the 700 mhz to 1 ghz specified rf frequency range. using the ad8340 as a single - sideband modulator and measuring the resulting s ideband suppression is a good gauge of how the quadrature accuracy is maintained over rf fr e quency. a typical plot of sideband suppression from 500 mhz to 1.5 ghz is shown in figure 28 . the level of sideband su p pres sion degradation outside the 700 mhz to 1 ghz specified range is subject to manufacturing process vari a tions. 04699-028 0 ?5 ?10 ?15 ?20 ?25 ?30 ?35 500 1500 1400 1300 1200 1 100 1000 900 800 600 700 frequenc y (mhz) sb suppression (dbc) figure 28 . sideband suppression vs. frequency rev. c | page 11 of 20
a d8340 data sheet applications information using the ad8340 the ad8340 is designed to operate in a 50 ? impedance sy s tem. figure 30 illustrates where the rf input is driven in a s ingle - ended fashion while the differential rf ou t put is converted to a single - ended output with a n rf balun. the baseband controls for the i and q channels are typically driven from differential dac outputs. the power supplies, vprf and vps2, should be byp assed appropriately with 0.1 f and 100 pf capacitors. low inductance grounding of the cmop and cmrf common pins is essential to prevent unintentional peaking of the gain. rf input and matchin g the input impedance of the ad8340 is defined by the chara c teris - tics of the polyphase network. the capacitive component of the network causes its impeda nce to roll off with frequency , albeit at a slower rate than 6 db/octave. with matching i n ductors on the order of 5.6 nh in series with each of the rf inputs, rfip and rfim, a 50 ? match is achieved with a return loss of >10 db over the operating frequency range. different matching inductors can improve matching over a narrower frequency range. the single - end ed and differential input i m pedances are exactly the same. 04699-029 50 100pf rf rfim rfi p rc phase 5.6nh 100pf 5.6nh ~1vdc figure 29 . rf input interface to the ad8340 showing coupling capacitors and matching inductors the rfip and rfim should be ac - coupled through low loss series capacitors as shown in figure 29 . the internal dc levels are at approximately 1 v. for single - ended operation, one input is driven by the rf signal and the other inp ut is ac grounded. 04699-0-030 ibb p ibbm vps2 dso p qbb p qbbm vps2 vps2 vprf cmrf rfim rfi p cmo p cmo p rfom rfo p qfl p qflm cmo p cmo p cmrf vprf ifl p iflm ad8340 c12 (see text) c 1 1 (see text) c8 0.1f l3 5.6nh c6 100pf l4 5.6nh c5 100pf ibbm ibb p v p rf input v p qbb p qbbm l1 120nh l2 120nh c14 0.1f c10 0.1f v p c18 100pf c17 100pf etc1-1-13 rf output a b output disable v p v p c1 0.1f c3 0.1f c2 100pf c7 100pf c4 100pf c9 100pf figure 30 . basic connections rev. c | page 12 of 20
data sheet ad8340 rf output and matchi ng the rf outputs of the ad8340 , rfop , and rfom, are open collectors of a transimpedance ampli fier that need s to be pulled up to the positive supply, preferably with rf chokes , as shown in figure 31 . the nominal output impedance looking into each individual output pin is 25 ?. consequently, the di f ferential output impedance is 50 ?. 04699-031 50 differentia l 100pf 1:1 rf output rfom rfo p r t r t 120nh 100pf v p g m i sig figure 31 . rf output interface to the ad8340 showing coupling capacitors, pull - up rf chokes, and balun because the output dc levels are at the positive supply, ac coupling capacitors are usually needed between the ad8340 outp uts and the next stage in the system. a 1:1 rf broadband output balun, such as the etc1 - 1 - 13 (m/a - com), converts the differential output of the ad8340 into a single - ended signal. note that the lo ss and balance of the balun directly impact the apparent output power, noise floor, and gain/phase errors of the ad8340 . in critical applications, narrow - band baluns with low loss and superior ba lance are recommended. if the output is taken in a single - ended fashion directly into a 50 ? load through a coupling capacitor, there is an impe d ance mismatch. this can be resolved with a 1:2 balun to convert the single - ended 25 ? output imped ance to 50 ?. if loss - of - si g nal swin g is not critical, a 25 ? back termination in series with the output pin can also be used. the unused output pin must still be pulled up to the positive supply. the user can load it through a coupling capacitor with a dummy load to preserve balance. the ga in of the ad8340 when the output is single - ended varies slightly with the dummy load value , as shown in figure 32. 04699-032 frequenc y (mhz) ?0.5 ?1.0 ?5.5 gain (db) 1000 ?3.5 ?4.0 ?4.5 ?5.0 ?2.5 ?3.0 ?1.5 ?2.0 ?6.0 900 800 700 r l2 = short r l2 = 50 r l2 = open figure 32 . g ain of the ad8340 using a single - ended output with different dummy loads, r l2 on the unused output the rf output signal can be disabled by raising the dsop pin to the positive supply. the shutdow n function provides >40 db attenuation of the input signal even at full gain. the interface to dsop is high impedance , and the shutdown and turn - on r e sponse times are <100 ns. if the disable function is not needed, the dsop should be tied to ground. drivi ng the i - q baseband controls the i and q inputs to the ad8340 set the gain and phase b e tween input and output. these inputs are differential and should normally have a common - mode level of 0.5 v. however, when differentially driven, the common mode can vary from 250 mv to 750 mv while still allowing full gain control. each input pair has a nominal input swing of 0.5 v differential around the common - mode level. the maximum gain of unity is achiev ed if the differential voltage is equal to +500 mv or ?500 m v. therefore, with a common - mode level of 500 mv, ibbp and ibbm each swing s between 250 mv and 750 mv. the i and q inputs can also be driven with a single - ended si g nal. in this case, one side of each input should be tied to a low noise 0.5 v voltage source (a 0.1 f decoupling capacitor lo cated close to the pin is recommended), while the other input swings from 0 v to 1 v. differential drive generally offers sup e rior even - order distortion and lo wer noise than single - ended drive. the bandwidth of the baseband controls exceeds 200 mhz even at full - scale baseband drive. this allows for very fast gain and phase modulation of the rf input signal. in cases where lower modulation bandwidths are accepta ble or desired, external filter capacit ors can be connected across pin iflp to pin iflm , and across pin qflp to pin qflm , to reduce the ingress of base - band noise and spurious signal into the control path. the 3 db bandwidth is set by choosing c flt accord ing to the following equation: pf 5 . 0 nf 10 khz 45 db 3 u eternal c f this equation has been verified for values of c flt from 10 pf to 0.1 f (bandwidth settings of approximately 4.5 khz to 43 mhz). rev. c | page 13 of 20
a d8340 data sheet interfacing to high speed dac s the ad977x family of dual dacs is well suited for driving the i and q vector controls of the ad8340 . while these inputs can in general be driven by any dac, the differential outputs and bias level of the analog devices txdac ? family allow for a direct connection between dac and modulator. the ad977x family of dual dacs has differential current ou t puts. the full - scale current is user programmable and is usually set to 20 ma, that is, each output swings from 0 ma to 20 ma. the basic interface between the ad9777 dac outputs and the ad8340 i and q inputs is shown in figure 33 . the r esistors r1 and r2 set the dc bias level according to the equation: bias level = average output current r1 for example, if the ful l - scale current from each output is 20 ma, each output will have an average current of 10 ma. ther e fore , to set the bias level to the recommended 0.5 v, r1 and r2 should be set to 50 ? each. r1 and r2 should always be equal. if r3 is omitted, this result s in an available swing from the dac of 2 v p - p differential, which is twice the maximum vol t age range required by the ad8340 . dac resolution can be maximized by adding r3, which scales down this v oltage a c cording to the following equation: ( ) ( ) ? ? ? ? ? ? + ? + = ? r3 r2 r2 r3 r2 r1 i swing scale full max 1 2 optiona l lo w - p ass fi l ter 04699-033 r1 r2 r3 i outb2 i ou t a2 qbbm qbb p i outb1 i ou t a1 ibbm ibb p ad9777 ad8340 optiona l lo w - p ass fi l ter r1 r2 r3 figure 33 . basic ad9777 to ad8340 inter face 04699-034 r3 130 50 55 60 65 70 75 80 85 90 100 105 1 15 120 1 10 125 95 differentia l peak- t o-peak swing (r3) 1.15 1.08 1.10 1.13 1.00 1.02 1.05 0.95 0.97 0.88 0.90 0.92 0.77 0.80 0.82 0.85 0.70 0.75 0.72 figure 34 . peak - to - peak dac output swing vs. swing scaling resistor r3 (r1 = r2 = 50 ) figure 34 shows the relationship between the value of r3 an d the peak baseband voltage with r1 and r2 equal to 50 ? . figure 34 shows that a value of 100 ? for r3 pr o vide s a peak - to - peak swing of 1 v p - p differential into the ad8340 i and q inputs. when using a dac, low - pass image reject filters are typically used to eliminate the nyquist images produced by the dac. they also provide the added benefit of eliminating broadband noise that might feed into the modulator from the dac. cdma2000 application to test the compliance to the cdma2000 base station standard, a single - carrier cdma2000 test model signal (forward pilot, sync, paging, and six traffic as per 3gpp2 c.s0010 - b, table 6.5.2.1) was applied to the ad8340 . a cavity - tuned filter was used to reduce noise from the signal source being applied to the device. the 4.6 mhz pass band of this filter is apparent in the subsequent spectral plots (see figure 35 to figure 38) . figure 35 shows a plot of the spectrum of the output signal u n der nominal conditions. p out is equal to ?5 dbm and v i = v q = 0.353 v, that is , vibbp ? vibbm = vqbbp ? vqbbm = 0.353 v. adjacent channel power is measured in 30 k hz resolution bandwidth at 750 k hz and 1.98 mhz carrier offset. noise floor is measured at 4 mhz carrier offset. rev. c | page 14 of 20
data sheet ad8340 l v l nor s p an 10mhz 1mhz/div center 880mhz ?20 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ? 1 10 marker 2 [t1 noi] ?148.76dbm/hz 876.009615385mhz *rbw 30khz *vbw 30khz *swt 100ms * a tt 5db bs, 1x, c0 : adj channe l ref ?12dbm 04699-035 ?30 ch pwr ac p low ac p u p a l t1 low a l t1 u p ?5.17dbm ?60.94db ?60.08db ?86.40db ?86.80db marker 1 [t1 noi] ?148.89dbm/hz 884.006410256mhz sw p 50 of 50 2 offset 0.5 db 1 figu re 35 . output spectrum, single - carrier cdma2000 test model at ?5 dbm v i = v q = 0.353 v, acp measured at 750 khz and 1.98 m hz carrier offset, noise measured at 4 mhz carrier offset, input signal filtered using a cavity tuned filt er (pass band = 4.6 mhz) holding the i and q control voltages steady at 0.353 v, input power was swept. figure 36 shows the resulting output power, noise floor, and adjacent channel power ratio. noise floor is prese nted as noise in a 1 mhz bandwidth as defined by the 3gpp2 specification. 04699-036 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ac p ? dbc (30khz rbw) ?30 5 0 ?5 ?10 ?15 ?20 ?25 output power (dbm) ?30 ?90 ?70 ?60 ?80 ?50 ?40 ?100 noise ? dbm @ 4mhz carrier offset (1mhz rbw) ac p ? 750khz offse t , 30khz rbw ac p ? 1.98mhz offse t , 30khz rbw noise ? 4mhz offse t , 1mhz rbw figure 36 . noise and acp vs. output power, single - carrier cdma2000 test model, v i = v q = 0.353, acp measured in 30 khz rbw at 750 khz and 1.98 m hz carr ier offset, noise measured at 4 mhz carrier offset the results s how that at an output power of 3 dbm, acp is still in compliance with the standard ( a d8340 data sheet evaluation board the evaluation board circuit schematic for the ad8340 is shown in figure 39. the evaluat ion board is configured to be driven from a single - ended 50 ? source. although the input of the ad8340 is differential, it may be driven single - ended with no loss of pe r formance. the low - pass corner frequency of the baseband i and q cha n nels can be reduced by installing capacitors in the c11 and c12 positions. the low - pass corner frequency for either channel is approximated by pf 5 . 0 nf 10 khz 45 db 3 + external c f on the evaluation oar the i an q asea n circuits are ientical so the following escription applies euall to each the connections an circuit configuration for the q asean inputs are escrie in tale the asean input of the a3 reuires a ifferential vol t age rive the evaluation oar is set up to allow such a rive connecting the ifferential voltage source to qbbp an qbbm the coon - oe voltage shoul e aintaine a t appro i atel v for this configuration uper 1 to uper shoul e reove the asean input of the evaluation oar can also e riven with a single - ene voltage in this case a ias level is provie to the unuse input fro potentioete r r1 installing either 1 or 2 setting s1 in position b isales the a3 output aplifier ith s1 set to position a the output aplifier is e n ale an an eternal voltage signal s uch as a pulse can e applie to the sop sma connector to eercise the output aplifier enaleisale function rev. c | page 16 of 20
data sheet ad8340 table 4 . evaluation board configuration options components description default conditions r7, r9, r11, r14, r15 , r19, r20, r21, c15, c19, w3, w4 i channel baseband interface . resistor r7 and resistor r9 can be installed to accommodate a baseband source that requires a specific terminating impedance. c15 and c19 are bypass capacitors. for single - ended baseband driv e, potentiometer r11 can be used to provide a bias level to the unused input (install either w3 or w4). r7, r9 = open r11 = p otentiometer, 2 k , 10 t urn s (bourns) r14 = 4 k ( size 0603) r15 = 44 k ( size 0603) r19, r20, r21 = 0 ( size 0603) c15, c19 = 0.1 f ( size 0603) w3 = jumper ( installed ) w4 = jumper ( open ) r1, r3, r10, r12, r13, r16, r17, r18, c16, c20, w1, w2 q channel baseband interface. see the i channel baseband interface description . r1, r3 = open r10 = potentiometer , 2 k , 10 turn s (bourns) r12 = 4 k ( size 0603) r13 = 44 k ( size 0603) r16, r17, r18 = 0 ( size 0603) c 16, c20 = 0.1 f ( size 0603) w1 = jumper ( installed ) w2 = jumper ( open ) c11, c12 baseband low - pass filtering. by adding capacitor c11 between qflp and qflm, and capacitor c12 between iflp and iflm, the 3 db low - pass corner frequency of the baseband int erface can be reduced from 230 mhz (nominal). see the equation in the evaluation board section . c11, c12 = open t1, c17, c18, l1, l2 output interface. the 1:1 bal un transformer, t1, converts the 50 differential output to 50 single - ended. c17 and c18 are dc blocks. l1 and l2 provide dc bias for the output. c17, c18 = 100 pf ( size 0603) t1 = etc1 -1- 13 (m/a - com) l1, l2 = 120 nh ( size 0603) l3, l4, c5, c6 input interface. the input impedance of the ad8340 requires 5.6 nh inductors in series with rfip and rfim for optimum return loss when driven by a single - ended 50 line. c5 and c6 are dc blocks. l3, l4 = 5.6 nh ( size 0402) c5, c6 = 100 pf ( size 0603) c2, c4, c7, c9, c14, c1, c3, c8, c10, r2, r4, r5, r6 supply decoupling. c2, c4, c7, c9 = open ( size 0603) c1, c3, c8, c10, c14 = 0.1 f ( size 0603) r2, r4, r5, r6 = 0 ( size 0603) r8, sw1 out put disable interface. the output stage of the ad8340 is disabled by applying a high voltage to the dsop pin by moving sw1 to position b. the output stage is enabled by moving sw1 to position a. the output disable function can also be exercised by applying an external high or low voltage to the dsop sma connector with sw1 in position a. r8 = 10 k ( size 0603) sw1 = spdt (position a, output enabled ) rev. c | page 17 of 20
a d8340 data sheet schematic and artwor k 04699-039 ibb p ibbm vps2 dso p qbb p qbbm vps2 vps2 vprf cmrf rfim rfi p cmo p cmo p rfom rfo p qfl p qflm cmo p cmo p cmrf vprf ifl p iflm ad8340 c12 (open) c 1 1 (open) c8 0.1f l3 5.6nh c6 100pf l4 5.6nh c5 100pf ibbm ibb p v p rfin v p qbb p qbbm l1 120nh l2 120nh c14 0.1f c10 0.1f c9 (open) v p c18 100pf c17 100pf rfo p b a c1 0.1f c7 (open) r5 0 r4 0 c3 0.1f c4 (open) t1 etc1-1-13 m/a-com sw1 r8 10k r2 0 c2 (open) v p test point gnd test point dso p vs r14 4k r 1 1 2k r15 44k c15 0.1f w4 r21 0 r19 0 w3 r20 0 r9 (open) r7 (open) c19 0.1f vs r12 4k r10 2k r13 44k r6 0 c16 0.1f w2 r17 0 r16 0 w1 r18 0 r1 open r3 open c20 0.1f figure 39 . evaluation board schematic rev. c | page 18 of 20
data sheet ad8340 04699-040 figure 40 . component side layout 04699-0-041 figure 4 1 . component side silkscreen rev. c | page 19 of 20
a d8340 data sheet outline dimensions 0.50 bsc 0.50 0.40 0.30 0.30 0.25 0.20 compliant to jedec standards mo-220-wggd-8. 06- 1 1-2012- a bot t om view top view exposed pa d pin 1 indic a t or 4.10 4.00 sq 3.90 sea ting plane 0.80 0.75 0.70 0.20 ref 0.25 min coplanarity 0.08 pin 1 indic a t or 2.20 2.10 sq 2.00 1 24 7 12 13 18 19 6 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.05 max 0.02 nom figure 42 . 24 - lead lead frame chip scale package [lfcsp _ w q ] 4 mm 4 mm body, very very thin quad (cp - 24 - 1 0 ) dimensions shown in millimeters ordering guide model 1 , 2 temperature range package description package option ordering quantity ad8340acpz - wp ?40c to +85c 24- lead lead frame chip scale package [ lfcsp _w q] cp -24-10 64 ad8340acpz - reel7 ?40c to +85c 24- lead lead frame chip scale package [lfcsp_ w q] cp -24-10 1,500 ad8340 - eval z evaluation board 1 1 z = rohs compliant part. 2 wp = waffle pack. ? 2004 C 201 4 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d04699 - 0- 3/14(c) rev. c | page 20 of 20

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